(a) Field of the Invention
The present invention relates to a SRAM generating an echo clock signal and, more particularly, to a SRAM including an echo clock generator for generating an echo clock signal at the timing of the output of read data.
(b) Description of the Related Art
Recent developments of the performance of personal computers are partly due to a pipe-line processing and burst read SRAM (PBSRAM) which is used as a secondary cache memory in the personal computers. With the developments of the high-speed capability of the personal computers, the PBSRAM is also requested to have a higher-speed operational capability.
In a double data rate PBSRAM wherein two cell data are read out at a single clock cycle, the data are output at the rate corresponding to the frequency which is double the operational frequency of the PBSRAM. For example, for an operational frequency of 250 MHz or a clock cycle of 4 ns (nanosecond) of the DDR-PBSRAM, the clock access rate corresponds to 2 ns or 500 MHz.
A new type of PBSRAM generates a reference signal called "echo clock signal", which informs the timing of the output of read data to the CPU when the read data is delivered from the PBSRAM, thereby compensating the irregularity of the output timing of the read data.
FIG. 1A shows a timing chart for the echo clock signal together with the read data in a single data rate PBSRAM (SDR-PBSRAM). In the drawing, CLK, ADD, AC and GW are external clock signal, address signal, address control signal and write enable signal, respectively, which are supplied from outside the PBSRAM. If the write enable signal GW assumes a high level when the address control signal AC is at a low level, the PBSRAM operates for reading data from memory cells, whereas if the write enable signal GW assumes a low level when the address control signal AC is at a low level, the PBSRAM operates for writing data to the memory cells.
The PBSRAM delivers a read data DQ and an echo clock signal KQ to the CPU in a read cycle. More specifically, the PBSRAM first fetches an address A1 at a rising edge "a" of the clock signal CLK, delivers read data DQ11 from the memory cell having the address A1 together with an echo clock KQ signal at a next rising edge "b". The PBSRAM also delivers read data DQ12 to DQ14 from the addresses succeeding the address A1 together with respective echo clock signals Kq at the succeeding rising dges "c" to "e", thereby executing a burst read operation. similarly, the PBSRAM fetches a next address A2 at a next rising edge "f" and delivers read data DQ21, DQ22, . . . from the addresses starting from the address A2 together with the echo clock signals KQ at the succeeding rising edges of the clock signal CLK.
In the SDR-PBSRAM, the rising edge of the echo clock signal KQ is used for a reference timing for compensating the irregularity of the output timing of the read data DQ. Thus, it is preferable that the timing difference TCHQV or TCHQX between the rising edge of the echo clock signal KQ and the start or end of the level shift caused by the corresponding read data DQ be as small as possible, in view of suppressing the irregularity of the timing difference between the read data and the echo clock signal.
FIG. 1B shows a timing chart for the echo clock signal together with the read data in a double data rate PBSRAM (DDR-PBSRAM). In the DDR-PBSRAM, the timing of output of the read data resides at a rising edge of the echo clock signal KQ as well as a falling edge of the echo clock signal KQ. More specifically, for the read data DQn delivered at the timing of a rising edge of the echo clock signal KQ, the rising edge is the reference to the output timing of the read data, whereas for the read data DQm delivered at the timing of a falling edge of the echo clock signal KQ, the falling edge is the reference to the output timing of the read data. Thus, it is preferable that the timing difference TCHQV or TCLQV between a rising edge of the echo clock signal KQ and the start of the level shift caused by the read data DQ as well as the timing difference TCLQX or TCHQX between a falling edge of the echo clock signal KQ and the start of the level shift caused by the read data DQ be as small as possible.
With the development of higher-operational speed and larger number of bits in data processing by the personal computers, it is a principal subject of the DDR-PBSRAM to obtain an optimum timing between the output of the read data DQ and the echo clock signal KQ, in view that DDR-PBSRAM has a double read rate.
FIG. 2 shows a layout of a conventional DDR-PBSRAM. The DDR-PBSRAM includes a memory cell array 11 including a plurality of memory cells arrayed in a matrix, and a peripheral circuit for controlling the read/write operation for the memory cell array 11. The external clock signal CLK fed through the external pad 10 is used for generating an internal clock signal CLKT which is in phase with the external clock signal CLK and controls the data output sections 2a to 2h and echo clock generators 3a to 3d.
In the exemplified PBSRAM, each of the data output sections 2a to 2h includes four output members. The large number of the output members and the echo clock generators 3a to 3d disposed in a chip causes a distortion in the internal clock signal CLKT. The distortion in the internal clock signal CLKT generates a timing difference between a group of read data DQ13 o DQ16 and DQ17 to DQ20 output from the output sections 2e and 2a near the pad 10 and a group of read data DQ1 to DQ4 and DQ29 to DQ32 output from the output sections 2h and 2d far from the pad 10, as well as a timing difference between the echo clock signals KQ.
The timing difference as described above may be alleviated by the depicted configuration wherein the internal clock signal CLKT is subjected to buffering by using inverters 4a to 4e disposed for this purpose to generate CLKT1 to CLKT4 which are in phase with the external clock signal CLK.
In this situation, it is important to reduce the timing difference between the echo clock signal KQ1 to KQ4 supplied through the echo clock generator 3a to 3d and the read data DQ1 to DQ32 supplied through the data output sections 2a to 2h. This means that the locations of the data output sections 2a to 2h and the echo clock generators 3a to 3d are important as viewed from the input pad 10.
FIG. 3 shows example of the echo clock generators 3a to 3d and the data output sections 2a to 2h in a conventional PBSRAM. The echo clock generator designated by numeral 30 includes a delay gate 31 and an output buffer 32, whereas the data output section designated by numeral 20 includes a data register 21 for latching the data WRB read from a memory cell 23 by a sense amplifier 24 based on the timing of the internal clock signal CLKT, and an output buffer 22.
The output buffer 22 of the data output section 20 receives data WRB stored in the data register 21, delivers the read data DQ at a high level of the data control signal OE and stops the read data DQ at a low level of the data control signal OE.
The output buffer 32 of the echo clock generator 30 iteratively outputs the echo clock signal KQ. Thus, the control signal for the output buffer 32 corresponding to the data control signal OE for the output buffer 22 is fixed to the source potential for enabling the output buffer 32 at any time, as shown in FIG. 3.
The delay gate 31 adjusts the timing of the echo clock signal KQ to be concurrent with the occurrence of the read data. The register 21 includes a master latch and a slave latch cascaded in this order. The data register 21 latches the data WRB at the rising edge of the internal clock signal CLKT and holds therein the data for one clock cycle until the next rising edge of CLKT.
In operation, when a data WRB is latched by the master latch and received in the slave latch of the data register 21 at the rising edge of CLKT, the data WRB in the slave latch is delivered to the output buffer 22 as a read data DQ. This operation of the data register 20 is called "data change" from data WRB to the read data DQ triggered by the rising edge of CLKT.
The delay gate 31 is disposed for adjustment of the timing of the echo clock signal KQ so that the rising edge of the echo clock signal KQ is made concurrent with the timing of the data change in the data register 21 triggered by the rising edge of the internal clock signal CLKT.
In the conventional PBSRAM, the circuit configuration of the data register 21 is different from that of the delay gate 31. This generates an undesirable irregularity in the timing difference between the rising edge of the echo clock signal KQ delivered from the output buffer 32 and the completion of data change in the data register 21 irrespective of the timing adjustment by the delay gate 31, due to the change in the ambient temperature, source voltage etc.
FIG. 4 shows another echo clock generator 30A proposed for alleviating the timing difference generated in the circuit of FIG. 3. The echo clock generator 30A of FIG. 4 includes an output buffer 32 and a pair of latches 33A and 33B which are similar to the latches provided in the data register 21.
The latch. 33A is controlled by the internal clock signal CLKT to latch a high level signal (or source potential) whereas the latch 33B is controlled by a complementary clock signal CLKB of the internal clock signal CLKT to latch a low level signal (or ground level).
In operation of the echo clock signal 30A, the latch 33A latches a high level signal at a rising edge of the internal clock signal CLKT and the high level signal is delivered to the output buffer 32, whereby the output buffer 32 delivers a high level of the echo clock signal KQ.
The echo clock signal KQ remains at a high level so long as the internal clock signal CLKT assumes a high level. In this period of the high level of the internal clock signal CLKT, the latch 33B does not transfer any signal to the output buffer 32 due to a low level of the complementary signal CLKB.
By providing the pair of latches 33A and 33B in the echo clock generator 30A, the echo clock generator 30A generates an echo clock signal KQ in phase with the external cock signal CLK. That is, the latch 33A delivers a rising edge of the echo clock signal KQ by responding to the rising edge of CLKT whereas the latch 33B delivers a falling edge of the echo clock signal KQ by responding to the rising edge of CLKB.
As a result, the interval between the rising edge of CLKT and the rising edge of the echo clock signal KQ (or the timing of the data change) as well as the interval between the rising edge of CLKB and the falling edge of the echo clock signal KQ does not depend on the frequency of the external clock signal CLK.
In other words, the access time between the rising edge of CLKT or CLKB and the timing of the echo clock signal KQ is fixed at a constant and thus does not depend on the frequency of the external clock signal CLK.
On the other hand, in the data output section 20, the data WRB input to the output register 21 is random data read from the memory cell 23, and may be delayed during the transfer of data WRB depending on the conditions of the data path along the sense amplifier 24 and the output register 21.
Accordingly, if the external clock signal CLK has a higher frequency, a time margin for latching the data WRB by the output register 21 is smaller, and in a critical case, the previous data is already transferred to the output buffer 22 before the subject data is transferred to the slave latch of the output register.
The detail of the data register 21 is shown in FIG. 5A. If an input data WRB is latched in the data register 21 at a rising edge of the internal clock signal CLKT, the access time consumed between the rising edge of CLKT and the data change from the input data "IN" to the output of the data "OUT" has a time delay of 0.1 ns (nanosecond) compared to an ordinary operation wherein input data "IN" is latched by the data register 21 with a sufficient time margin.
FIG. 5B shows the access time of the memory device using the data register 21 shown in FIG. 5A plotted against the clock period of the external clock signal CLK.
In the memory device using the data register of FIG. 5A, for the external clock signal CLK having a clock period longer than 3.0 ns, the access time remains at a constant of 2.0 ns due to the time margin for the latching by the data register 21. However, for the external clock signal CLK having a shorter critical clock period of 2.9 ns, the access time rises up to 2.1 ns, as shon in FIG. 5B.
The data register may have a configuration of FIG. 6A for responding to an external clock signal having a higher operational frequency, wherein the data register 21A has a delay gate 27 for delaying the internal clock signal CLKT supplied to the master latch 28 compared to the CLKT supplied to the slave latch 29. In this case, the access time rises from 2.1 ns as described above by the delay time of the delay gate 27, when the input data is latched in the data register 21A by responding to the rising edge of the internal clock signal CLKT input to the master latch 28.
FIG. 6B shows the access time for the PBSRAM having the data register of FIG. 6A plotted against the clock period of the external clock signal CLK. In this case, the access time is constant so long as the clock period of the external clock signal CLK is above 3.0 ns. However, the access time rises up to 2.4 ns for the external clock signal CLK having a shorter critical clock period of 2.6 ns.
More specifically, if the external clock signal CLK has a critical clock period, which is critical for controlling the data output section, the access time involves a delay time of 0.4 ns compared to an ordinary access time of 2.0 ns. And if the delay time of 0.1 ns described above is considered for the delay time of 0.4 ns, a delay time of 0.3 ns is generated due to the delay to the internal clock signal CLKT input to the data output section. Accordingly, the delay gate 27 shown in FIG. 6A improves the operation of the data output section by the delay time of the delay ate 27, wherein the delay gate 27 has a delay time of 0.3 ns in his case.
In the PBSRAM including the data register of FIG. 6A, the access time for the echo clock signal KQ does not depend on the frequency of the external clock signal CLK, whereas the access time for the read data DQ depends on the frequency of the external clock signal CLK for a higher frequency of the external clock signal. Thus, an irregularity is generated in the output timing between the echo clock signal KQ and the read data DQ.